(a) Field of the Invention
The present invention relates to a liquid crystal display and a method for fabricating the same and, more particularly, to a liquid crystal display showing good performance characteristics.
(b) Description of the Related Art
A liquid crystal display is one of the flat panel displays that have been currently used in a most extensive manner. Such a liquid crystal display basically has two glass substrates with electrodes for generating electric fields, a liquid crystal layer sandwiched between the substrates, and polarizing plates externally attached to the substrates. When voltage is applied to the electrodes, the liquid crystal molecules are re-oriented to thereby control light transmission.
One of the substrates is provided with an array of thin film transistors (TFTs) for switching voltages applied to the electrodes.
The TFT array substrate has a plurality of gate and data lines proceeding in the horizontal and vertical directions, respectively. The data lines cross over the gate lines to thereby define pixel areas, and pixel electrodes are formed at the pixel areas. The TFTs control picture signals transmitted thereto through the data lines in accordance with scanning signals transmitted thereto through the gate lines, and sends the picture signals to the pixel electrodes. The display area may be outlined by the set of the pixel areas surrounded by the wiring lines. A plurality of gate and data pads are formed at the TFT array substrate external to the display area while being connected to the gate and data lines. The gate and data pads are directly connected to external driving ICs to receive scanning signals and picture signals from the outside, and transmit the signals to the relevant signal lines.
A gate printed circuit board, and a data printed circuit board are provided external to the TFT array substrate to transmit relevant signals thereto. A data signal transmission film interconnects the TFT array substrate with the data printed circuit board, and a data driving IC is mounted on the data signal transmission film to convert electrical signals into data signals, and send the data signals to the data pads and the data lines. Furthermore, gate signal transmission films connect the TFT array substrate with the gate printed circuit board, and gate driving ICs are mounted on the gate signal transmission films to convert electrical signals into gate signals, and send the gate signals to the gate pads and the gate lines.
Gate signal pads, and data signal pads are aligned with the gate and data pads in a one to one correspondence, and connected thereto through thermal compression process using an anisotropic conductive film (ACF).
Meanwhile, the gate printed circuit board may be omitted. In this case, the data printed circuit board generates gate signals, and sends the signals to the gate signal transmission film. Gate signal wires for transmitting the gate signals are formed at the data signal transmission film connected to the data printed circuit board. Gate signal interconnection wires are formed at the TFT array substrate to connect the gate signal lines of the gate signal transmission films with the gate signal wires. The gate signal wires, and the gate signal interconnection wires are connected to each other to receive gate signals from the data printed circuit board, and transmit the signals to the gate driving ICs.
However, in the above structure, corrosion should not occur at both pad portions of the gate signal interconnection wires interconnecting the gate signal lines and the gate signal wires to obtain good contact characteristics, and the thermal compression process using the ACF should be performed in a stable manner.
It is an object of the present invention to provide a liquid crystal display which involves good contact characteristics.
It is another object of the present invention to provide a liquid crystal display where gate signal interconnection pads are covered by leads of gate and data signal transmission films, or stepped difference at the contact poritons is minimized.
These and other objects may be achieved by a liquid crystal display with an insulating substrate. The substrate is overlaied with a plurality of gate lines, and a plurality of data lines crossing over the gate lines to define pixel areas. A gate signal interconnection line assembly is formed at the substrate. The gate signal interconnection line assembly is provided with gate signal interconnection lines, and first and second gate signal interconnection pads connected to both ends of the gate signal interconnection lines to relay gate electrical signals to the gate lines. Insulating layers are formed on the substrate while bearing first and second contact holes exposing the first and second gate signal interconnection pads. Gate signal transmission films are attached to the substrate while each mounting a gate driving integrated circuit thereon to receive gate electrical signals and send gate signals to the gate lines. Each gate transmission film has first gate signal wires, and first gate signal leads connected to the first gate signal interconnection pads through the first contact holes. Data signal transmission films are attached to the substrate with second gate signal wires, and second gate signal leads connected to the second gate signal interconnection pads through the second contact holes. The first or the second gate signal lead completely covers the first or the second contact hole at least in the longitudinal direction of the lead.
The liquid crystal display further includes a printed circuit board connected to the data signal transmission films to send the gate and data electrical signals to the gate driving integrated circuits and the data driving integrated circuit.
Pixel electrodes are formed on the insulating layer at the pixel areas. First and second subsidiary gate signal interconnection pads are formed at the same plane as the pixel electrodes while covering the first and second contact holes. The first and second subsidiary gate signal interconnection pads are positioned between the first and second gate signal interconnection pads and the first and second gate signal leads, respectively.
The insulating layers are formed with a gate insulating layer covering the gate lines, and a protective layer covering the data lines over the gate insulating layer. The first or the second gate signal lead completely covers at least one side of each contact hole in the longitudinal direction. The gate signal interconnection line assembly may be formed at the same plane as the gate lines or the data lines, and provided with first gate signal interconnection lines placed at the same plane as the gate lines, and second gate signal interconnection lines placed at the same plane as the data lines. The first and the second gate signal interconnection lines are connected to each other via the first and second subsidiary gate signal interconnection pads.